Book Description
The implementation of test on today's products requires that we understand extensively all areas pertinent to test including simulation and integration with CAD. The detection of faults can be accomplished using different techniques which are detailed in this publication including BIT (Built-in Test) and SCAN. Information within this publication will detail about testing of ICs and circuitry, setting up for bare board and in-circuit test, building the test fixtures using CAD data, programming, detecting failures, design needs for test, and all about all kinds of testing techniques for different types of circuitry. It is a publication that will be used as a constant reference to address testing issues.

Who Will Benefit
This book will be of immense value to both test engineers as well as CAD designers, and those involved in product testing, fabrication, troubleshooting and debug of high-speed products.

Table of Contents

1- TECHNICAL TRENDS

• IC Devices, PCB's
• CAD Simulation
• New Methods of Testing
• RISC/CISC
• Tester Speed

2- SIMULATION

• Stimulus Patterns, Post Processing, Philosophy
• Automatic & Manual Test Pattern Generator
• DWG Operation, Transceiver Pin
• Complex Chips & Boards
• Run Time
• Building Testers & Software
• Hardware Modelling, Design Verifiers, Back Tracing
• Simulation Example
• New Advances in Simulation- IEEE 1076
• Verilog/VHDL
• Simulator/ATE Timing Packages
• Failure Modes Not Predicted by Simulation

3- INTEGRATING CAD and TESTERS

• Minimising Software
• Integrating the Factory
• Bare Board Test Integration
• Continuity Test Integration
• In-Circuit Test Integration

4- BUILT-IN TEST

• Detecting Operation Failures, Economics, Bypassing Levels of Test
• Performing Optimum ESS
• Auto Interfaced BIT, BIT Sequences/Strategy
• Testing Alive & Dead Boards
• Testing Microprocessors
• Testing RAM, ROM, I/O
• Testing Analogue Stimuli
• Testing the System
• Testing Digital Boards, D/A Boards, ADC, DAC

5- TESTING SMT

• Components, Bare Boards, ICT
• Robotic and Functional Complexity Trends
• 2 PCB Vs 1 PCB Law
• Controlling Bus & Clocks
• Clam Shell Fixtures- Accuracy, Skew, Failures, Visibility
• Bed Of Nails- Accuracy, Cells, Test Pads, PCB Layout
• Clock Control, Board Stress
• ICT vs. Functional- ICT Vs PPM, Lead Pitch, DFM, Pad Sizes
• PCB Accuracy/Errors
• Grids
• Probe Contamination and No-Clean Solder Paste
• ESD Concerns
• New Test Concepts
• Wireless Fixtures

6- SCAN

• Advantages/Disadvantages
• Types of Scan
• IEEE 1149.1 through 1149.5
• New Standards, The Boundary SCAN Cell
• Sample, Preload, Extest, Intest, BIST
• SCAN Tri-States, Logic, CPU, ASIC's
• Overhead Restrictions
• SCAN Test Limitations
• Future of Scan

7- SMT in the USER'S ENVIRONMENT

• Electrical Guides
• Test Points
• ADC's and DAC's
• Frequency Monitoring, Analogue Monitoring
• RAM and PROM Diagnostics
• BIT Reference Testing
• DFT

Author: Robert Hanson
Edition: 1996
Pages: 243 pages 8.5" x 11"

Price: Quote me

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